1. Field of the Invention
The present invention relates to a semiconductor memory device and, in more particular, to a structure for carrying out voltage stress acceleration testing such as burn-in testing. More specifically, the present invention relates to fast and highly reliable voltage stress acceleration testing of dynamic semiconductor memory devices.
2. Description of the Background Art
In manufacturing and then shipping semiconductor memory devices, the semiconductor memory devices are generally screened prior to shipping by revealing latent failures of the semiconductor memory devices, and thus semiconductor devices having the possibility of initial failure are removed to ensure the reliability of the shipped semiconductor memory devices. One of such screening methods is burn-in testing in which high temperature and high voltage are applied to a semiconductor device for operation of the semiconductor device. In the burn-in testing, a semiconductor device is operated with the applied voltage higher than a voltage practically applied and the ambient temperature higher than a temperature practically applied so that the semiconductor device experiences stress greater than that caused during the initial failure period under practical conditions within a short period of time, and any semiconductor devices having the possibility of initial operation failure are selected prior to shipping. Such screening testing efficiently eliminates a semiconductor device having the possibility of initial operation failure and thus improves reliability of products.
In a semiconductor device with large storage capacity, the number of word lines arranged corresponding to rows of memory cells is increased (8K word lines for a 64 M bit DRAM (Dynamic Random Access Memory), for example). When burn-in testing is carried out such that the same number of word lines as in the normal mode of operation are selected in one cycle, address scanning is performed and voltage stress is sequentially applied to the word lines, each word line is only selected once in 8K/n cycles, wherein n represents the number of word lines simultaneously selected in the normal operation mode. This reduces a time period during which voltage stress is applied to each word line. To apply sufficient voltage stress to each word line, word lines need be repeatedly selected and this increases burn-in testing time period.
Furthermore, the increase in number of word lines also increases the time required for burn-in testing.
In order to carry out such burn-in testing at high speed, a method has been proposed in which all word lines are simultaneously selected and direct-current voltage stress is applied to each word line (see Japanese Patent Laying-Open No. 4-225182).
FIG. 25 schematically shows a configuration of a main portion of a conventional semiconductor memory device. In FIG. 25, the conventional semiconductor memory device includes a plurality of memory cells MC arranged in a matrix of a plurality of rows and a plurality of columns, a plurality of word lines WL0-WLn arranged each corresponding to each row of memory cells and each connected to memory cells of a corresponding row, and a plurality of pairs of bit lines arranged each corresponding to each column of memory cells and each connected to memory cells of a corresponding column. FIG. 25 representatively shows one pair of bit lines BL and /BL.
Memory cell MC includes a memory capacitor MQ for storing information, and an access transistor MT formed of an n channel MOS transistor which is turned on in response to a signal potential on a corresponding word line (W0-WLn) to connect memory capacitor MQ to a corresponding bit line (BL or /BL). One elect rode node (a cell plate electrode) of memory capacitor MQ receives a constant cell plate voltage Vcp.
The conventional semiconductor memory device further includes an address buffer AB which buffers an externally applied address signal and generates an internal address signal, a row decoder RD which decodes an internal row address signal applied from address buffer AB to generate a word line select signal for selecting a word line corresponding to an addressed row, and a word line driver WD which responds to the word line select signal from row decoder RD to transfer a boosted voltage Vpp onto the selected word line. The voltage level of boosted voltage Vpp is higher than that of an operating power source voltage.
When a burn-in designation signal .phi.BRN applied via a pad PDa is activated, row decoder RD generates a signal selecting all word lines independently of the logic states of internal address signal bits applied from address buffer AB.
The semiconductor memory device further includes a Vpp generation circuit VPG which generates boosted voltage Vpp, and a switch circuit SWa which selects one of a voltage Ve applied from a pad PDb and a voltage from Vpp generation circuit VPG in response to burn-in mode designation signal .phi.BRN and transfers the selected voltage as boosted voltage Vpp to word line driver WD. Switch circuit SWa selects the voltage from Vpp generation circuit VGP in a mode of operation other than the burn-in (referred to as the normal mode of operation hereinafter), and selects voltage Ve externally applied via pad PDb in the burn-in mode.
The semiconductor memory device further includes a switch circuit SWb which selects one of a predetermined intermediate voltage Vb1 and a ground voltage Vss in response to burn-in mode designation signal .phi.BRN, and a bit line equalizer circuit BEQ provided for each pair of bit lines BL and /BL for transferring a voltage applied from switch circuit SWb to each of bit lines BL and /BL of a corresponding pair of bit lines when bit line equalizer circuit BEQ is activated. Switch circuit SWb selects intermediate voltage Vb1 in the normal mode of operation and ground voltage Vss in the burn-in mode. An operation of the semiconductor memory device shown in FIG. 25 in the burn-in mode will now be described with reference to FIG. 26.
In the burn-in mode, burn-in mode designation signal .phi.BRN applied to pad PDa is activated at high (H) level. In response to the activation of burn-in mode designation signal .phi.BRN, switch circuit SWa selects external voltage Ve applied to pad PDb and applies external voltage Ve to word line driver WD. Switch circuit SWb selects ground voltage Vss instead of intermediate voltage Vb1. Bit line equalizer circuit BEQ is activated via a path (not shown) in response to the activation of burn-in mode designation signal .phi.BRN and holds both bit lines BL and /BL at the ground voltage Vss level.
In this state, row decoder RD is activated in response to activation of a row address strobe signal /RAS (not shown) and performs a decoding operation. In the decoding operation, burn-in mode designation signal .phi.BRN is in an active state and row decoder RD generates a signal selecting all word lines WL0-WLn independently of the logic state of an address signal bit applied from address buffer AB.
In response to the row select signal from row decoder RD, word line driver WD transfers external voltage Ve applied from pad PDb onto word lines WL0-WLn. Word lines WL0-WLn receive external voltage Ve and voltage stress for the gate of access transistor MT of memory cell MC is accelerated. Meanwhile, the potential of each of bit lines BL and /BL is set at low (L) level to also accelerate the voltage stress between the gate and the drain of access transistor MT.
By constantly applying external voltage Ve to word lines WL0-WLn, direct-current voltage stress is applied and voltage stress can be continuously applied to word lines WL0-WLn during the period of the burn-in mode to aim carrying out of efficient burn-in. Furthermore, since all word lines WL0-WLn are simultaneously driven into selected state, the time period required for burn-in is reduced as compared with a case in which word lines are successively selected to receive voltage stress.
When the burn-in mode is completed, word lines WL0-WLn are all driven into non-selected state (in response to inactivation of row address strobe signal /RAS). Then, burn-in mode designation signal .phi.BRN is set at an inactive state of L level and switch circuit SWb is set to select intermediate voltage Vb1. After completion of the operation in the burn-in mode and when the semiconductor memory device is in a standby state, bit line equalizer circuit BEQ is in active state and bit lines BL and /BL are precharged at the intermediate voltage VBL level. Row decoder RD is also set to perform a decoding operation in response to an address signal supplied from address buffer AD.
Since an externally applied voltage is used to transfer a driving voltage to all of word lines in burn-in testing, all of the word lines can be held in selected state without being affected by the driving capability of on-chip Vpp generation circuit VPG. In driving all of the word lines into selected state, however, current is supplied from pad PDb to drive all of the word lines into selected state and large current flow is thus caused. The large current can cause migration of aluminum in a signal line transferring a boosted voltage to word line driver WD and it can disadvantageously cause deterioration of the high voltage transferring line. That is, a defect which has not existed is caused in burn-in testing and a satisfactory semiconductor memory device will be turned into a defective semiconductor memory device.
During the burn-in testing, bit lines BL and /BL receive ground voltage Vss. Meanwhile, cell plate voltage Vcp is maintained at a fixed voltage level. A stress condition accelerating voltage is applied between the gate and the drain of access transistor MT and voltage stress for access transistor MT thus can be accelerated. Meanwhile, ground voltage Vss of bit line BL or /BL is transferred to the other electrode (a storage node) of memory cell capacitor MQ. The level of cell plate voltage Vcp for memory cell capacitor MQ as well as bit line precharging voltage Vb1 is equal to the intermediate voltage level, which is a half of the voltage level of operating power supply voltage Vcc. Thus, the voltage stress for the memory capacitor is also accelerated.
When the voltage stress acceleration condition for the memory cell capacitor is not the same as that for the gate insulating film of the access transistor, reliability evaluation for the capacitor cannot be performed simultaneously with that for the access transistor. Meanwhile, cell plate voltage Vcp is, as is in a normal operation, maintained at a half of power supply voltage Vcc, and the word line driving voltage is set according to externally applied voltage Ve, so that the voltage stress acceleration condition for the memory capacitor cannot be the same as that for the access transistor and thus a reliability evaluation for the memory capacitor requires a voltage stress acceleration testing separated from a reliability evaluation for the access transistor.